The serial peripheral interface (SPI) is one of two independent serial communications subsystems included on the Motorola MC68HC11A8 microcontroller. As the name implies, the SPI is primarily used to allow a microcontroller unit (MCU) to communicate with peripheral devices. The central element in the Motorola serial peripheral interface system is a block containing the shift register and the read data buffer. The system is single buffered in the transmit direction and double buffered in the receive direction. This fact means that a subsequent data byte for transmission cannot be written to the shifter until the current data byte transmission is complete; however, received data is transferred into a parallel read data buffer so the shifter is free to accept a second serial character. As long as the first character is read out of the read data buffer before the next serial character is ready to be transferred, no write collision condition will occur.
A write collision occurs if a data register is written while a transfer is in progress. Since the data register is not double buffered in the transmit direction, writes to data register cause data to be written directly into the SPI shift register. Because this write corrupts any transfer in progress, a write-collision error is generated. The transfer continues undisturbed, and the write data that caused error is not written to the shifter. The write collision avoidance in the Motorola SPI causes a degradation in the data throughput. The software driver has to pinpoint the exact moment when to request a new data byte transmission. The software driver is located at the CPU level and overlooks all the write collision problems of all master-slave registers in the MCU-to-MCU communications. The software driver is not located at each local SPI, and therefore it takes time and sacrifices in the data throughput of the system.
FIG. 1 illustrates a schematic diagram of representative prior art SPI circuitry. The SPI subsystem 100 includes a serial master shift register 102, a serial slave shift register 110, and a parallel slave shift register 130. One problem inherent to such circuitry requires the software driver to wait for a current data byte transmission to complete and for other necessary control commands in order to avoid write collision.
Parallel data from the CPU (not shown) are loaded into a data input bus 101 DataInBus and into the serial slave shift register 110. Serial data are first shifted into the master shift register 102 when the master clock goes HIGH. As serial data is shifted serially from the serial master register 102 into the serial slave register 110, the previous parallel data from the CPU and data input bus 101 DataInBus is left shifted by one bit and into the serial master register 102. Only after all the data are shifted from the serial input 103 into the serial master register 102, and after previous data are shifted from the serial slave register 110 back to the serial master register 102, the subsequent data from the CPU are loaded in a parallel fashion into the serial slave register 110. A software driver (not shown) at the CPU monitors closely these data transmissions in order to avoid data corruption.
The SPI 100 also has a software driver (not shown), a bit counter to track the status of the SPI's transmission, and a finite state machine (FSM) controller to provide load control signals to the SPI, communicate “receive ready” signals to the CPU and report any write collision errors.
Write collision happens when the SPI 100 has not finished transmitting the current data byte from the serial master register 102 into the serial slave register 110, and the subsequent data byte has already transmitted into the serial slave register 110. In order to prevent write collision, the software driver must know when the current data byte is completely transmitted and wait for other control commands such as the write collision signal, receive save signal, receive ready signal, in order to allow the transmission of the subsequent data byte. Consequently, the clock signal is stretched out and the data throughput of the SPI 100 suffers.
There are attempts to resolve this primary drawback of a serial peripheral interface apparatus. One such attempt is disclosed in the U.S. patent application Ser. No. 4,816,996, entitled “Queued Serial Peripheral Interface for Use in Data Processing System” by Susan C. Hill et al. (hereinafter “The '996 patent). In the '996 patent, the improved serial peripheral interface reduces the amount of intervention required on the part of the controlling data processing device by using a memory means with queue pointer and data serializer coupled to master slave input/output buffers. The memory means store both received data, data to be transmitted, commands for each serial transfer. Each serial transfer is executed in accordance to a command specific to such transfer. The command alters the queue pointer to fit to such particular data byte and to improve the efficiency of the transfer, thus reducing the intervention from the controller to each data transfer. In other words, the serial peripheral interface of the '996 patent includes a memory means, a serializer, a command/control, a queue pointer, and input/output buffers to improve th serial transfer. The end result is that when the serial transfer is efficient, there is less intervention of the controller to accomplish a given data transfer.
There is a need for a simple, cost effective improvement of the throughput of the serial peripheral interface apparatus.